Moving object detection including background subtraction and morphological processing is a critical\nresearch topic for video surveillance because of its high computational loading and power\nconsumption. This paper proposes a hardware design to accelerate the computation of background\nsubtraction with low power consumption. A real-time background subtraction method is\ndesigned with a frame-buffer scheme and function partition to improve throughput, and implemented\nusing Verilog HDL on FPGA. The design parallelizes the computations of background update\nand subtraction with a seven-stage pipeline. A stripe-based morphological processing and\naccounting for the completion of detected objects is devised. Simulation results for videos of VGA\nresolutions on a low-end FPGA device show 368 fps throughput for only the real-time background\nsubtraction module, and 51 fps for the whole system, including off-chip memory access. Real-time\nefficiency with low power consumption and low resource utilization is thus demonstrated.
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